Silicon chips form the basis of most conventional computing. Semiconductor firms have been optimising their processes for decades and are able to fit billions of transistors onto a single chip. QCS Hub researchers at UCL are exploring how the same technology can also be used for quantum computing. Our goal is to use a scalable industry- compatible silicon platform to build dense,high-fidelity qubits and multi-qubit gates.
The ability to use quantum error correction is a key challenge in creating a fault tolerant quantum computer. Doing this requires a large number of qubits, and the opportunity to create devices with millions of qubits on a single chip would be a major breakthough. Our team has already measured simple spin in such devices and is working to overcome the challenges that would make this technology a practical solution.
Why silicon qubits?
Silicon spin qubits are promising candidates for realising large scale quantum processors, benefitting from a magnetically quiet host material and the prospects of leveraging the mature silicon device fabrication industry. Our work package aims to harness the decades and trillions of dollars of investment in perfecting fabrication techniques in CMOS.
The key strengths of silicon spin qubits are:
CMOS is a proven platform to produce billions of devices per chip with high yield and reproducibility.
Integration between quantum devices and classical control is possible on the same chip.
Long coherence times in the solid state (seconds for the electron spin; and hours for the nuclear spin)
Fault-tolerant fidelities, exceeding 99.5% for both single and two-qubit gates and exceeding 99% for measurement.
Fast gate speeds with single and 2-qubit gates demonstrated in ~100 ns
Inter-qubit spacing currently ~100 nm in silicon qubits means that a density of 107 - 108 qubits per cm2 could be achieved
What have we achieved so far?
Since the launch of the QCS Hub we have made a series of advances including:
Spin measurement in using CMOS compatible devices
We presented the first measurement of a single electron spin in a silicon device fabricated at the 300mm wafer scale. We measured a spin relaxation time (T1) of up to 9 seconds, amongst the longest measured for an electron spin in a solid-state device. [Ciriano et al., PRX Quantum 2, 010353 (2021)]
Resource estimation for quantum simulation
In the NISQ era, one possible task we can perform without quantum error correction using NISQ machines is the variational quantum eigensolver (VQE), due to its shallow depth. However, we found that implementing a 50-qubit Hubbard model VQE on a NISQ machine would potentially summer for major runtime challenges. We proposed a parallelisation approach called ‘multicore NISQ’ which lends itself to a silicon implementation due to the high qubit density. [Cai, Phys. Rev. Applied 14, 014059 (2020)]
A path to 2D nanowire arrays
We demonstrated capacitive coupling across neighbouring nanowires. This opens a potential route to 2D scaling of quantum dot arrays across nanowires. [Duan et al., Nano Lett 20, 7123 (2020)]
Using deep learning to understand and control qubit noise environment
Understanding the environment surrounding quantum systems is key to being able to use them as quantum sensors or qubits, but doing so accurately is challenging using traditional mathematical and experimental techniques. We showed how machine-learning techniques and specifically neural networks can be used to infer the qubit environment accurately using only simple and readily performed experimental measurements. This is important because it allows the design of bespoke control sequences to protect fragile quantum states from their particular environments for much longer than would otherwise be the case. [Wise et al., PRX Quantum 2, 010316 (2021)]
